For this type, two pattern display modes are available as follows.

• P1 (Display resolution 256x212, 2 layers)
• P2 (Display resolution 512x212)

Various highly advanced functions are available such as powerful sprite function and dual-layer independent omnidirectional scroll function.

For this type, four kinds of bit map display modes are available as follows. They are capable of providing display on the NTSC or PAL frequency monitor.

• B1 (Display resolution 256x212)
• B2 (Display resolution 384x240)
• B3 (Display resolution 512x212)
• B4 (Display resolution 768X240)

• Capable of doubling the resolution in the vertical direction by using the interlace.
• Up to 32,768 colors/pixel can be displayed.
• Built-in color palette (64 colors selected out of 32,768 colors)
• Omnidirectional smooth scrolling is possible.
• Superimposition and digitization are possible. (Video9000)
• Allows use of the monitor screen to the full extent in four directions as the display range by using the over-scan mode (B2, B4) in such application as for the telopper.
• Supports the high-speed hardware drawing commands such as the screen transfer, font color development and line.
• The hardware cursor display function is available.

For this type, two kinds of bit map display modes are available as follows. They can be displayed on the high resolution Monitor.

• B5 (Display resolution 640X400)
• B6 (Display resolution 640X480)

• Up to 16 colors/pixel can be displayed. (Selectable out of 32,768 colors depending on the color palette)
• Omnidirectional smooth scrolling is possible.
• Supports the high-speed hardware drawing commands such as the screen transfer, font color development and line.
• The hardware cursor display function is available.

• Built~in DA converter
• Linear RGB output
• Direct connection of CG ROM such as KANJI ROM is possible, but has not been implemented in Gfx9000 or Video9000. Further information regarding it is omitted from this manual.
• Useable VRAM: Dual port DRAM (The access time is 120nS, but 100nS for the B6 mode.)
  • 64Kx4
  • 128Kx8
  • 256Kx4
• As the VRAM capacity, 128KB, 256KB and 512KB configurations are possible.
• Capable of direct access from CPU to VRAM by means of the 16 bit bus.
• Use of the LCD panel (1 screen panel and single drive type of 2 screen panel) is possible.

To set a value in the register, have the register No. output at REGISTER SELECT port (P#4) and then the data at REGISTER DATA port (P#3).
To obtain the value from the register, have the register No. output at P#4 and then read P#3.
The register No. is specified by using the lower 6 bits of the value at P#4 and the bit 7 (MSB) functions as WII (Write Increment Inhibit) and bit 6 as RII (Read Increment Inhibit). If WII is "1", automatic increment of the register No. by writing the data to the register is prohibited. If RII is "1", automatic increment of the register No. by reading the data of the register is prohibited.

	b7	b6	b5	b4	b3	b2	b1	b0
P#4 (Write)	WII	RII	Register No. (R#n)
P#3 (Read/Write)	Register Data
	...

To write a value in VRAM, set the target address to VRAM Write Base Address registers (R#0-R#2) and have the data output at VRAM DATA port (P#0). As the bit 7 (MSB) of R#2 functions as AII (Address Increment Inhibit), if it is "1", automatic address increment by writing the data is inhibited.

To read the data of VRAM, set the target address to VRAM Read Base Address registers (R#3-R#5) and read in the data of VRAM DATA port (P#0). As the bit 7 (MSB) of R#5 functions as AII (Address Increment Inhibit), if it is "1", automatic address increment by reading in the data is inhibited.

The address can be specified up to 19 bits (512K bytes), with lower 8 bits set to R#0 (or R#3), center 8 bits to R#1 (or R#4) and upper 3 bits to R#2 (or R#5).

Note: Always the full address must be written. Specifying partial addresses will not work correctly.

• VRAM Write

	b7	b6	b5	b4	b3	b2	b1	b0
P#4 (Write)	0	0	0	0	0	0	0	0
P#3 (Write)	VRAM lower address								(R#0 set)
P#3 (Write)	VRAM center address								(R#1 set)
P#3 (Write)	AII	VRAM upper address							(R#2 set)
P#0 (Write)	Data
	...

• VRAM Read

	b7	b6	b5	b4	b3	b2	b1	b0
P#4 (Write)	0	0	0	0	0	0	1	1
P#3 (Write)	VRAM lower address								(R#3 set)
P#3 (Write)	VRAM center address								(R#4 set)
P#3 (Write)	AII	VRAM upper address							(R#5 set)
P#0 (Read)	Data
	...

The palette data can be set or checked by setting the palette No. and RGB specification to the palette pointer (R#14) and reading or writing to the palette data port (P#1).

The palette No. is specified by using the upper 6 bits of R#14 and RGB by using the lower 2 bits (R=0, G=1, B=2). The lower 2 bits constitute a ternary counter which undergoes automatic increment in the order of RGB through the port access. Setting these counter bits to 3 manually will cause the next palette write to be ignored and the counter to wrap around to 0 on the same palette number.

It's possible to partially update the palette colors as changes to either Red, Green or Blue values take effect immediately.

It should be noted that how the palette setting is actually displayed also depends on the palette control register (R#13) setting.

	b7	b6	b5	b4	b3	b2	b1	b0
P#4 (Write)	0	0	0	0	1	1	1	0
P#3 (Write)	Palette No.						0	0	(R#14 set)
P#1 (Write)	YS	-	-	RED data
P#1 (Write)	-	-	-	GREEN data
P#1 (Write)	-	-	-	BLUE data

With the necessary parameter set to the command registers, set the operation code. For transfer from CPU (or to CPU), the data is output to the command data port (P#2) by the amount required after this stage.

Only by reading the status port (P#5, Read Only), the status of the V9990 can be checked.

The cause of interrupt can be determined by reading the interrupt flag port (P#6). As the flag is not reset automatically, "1" should be written to the applicable bit to reset it.

The system control port (P#7) is only for writing. It can be used to reset the system and to select the master clock.

Pattern Display Function

Mode name	P1	P2
Master clock frequency	21.5MHz	21.5MHz
Pixel clock frequency	5.4MHz	10.7MHz
Horizontal cycle	15.7kHz (NTSC)	15.7kHz (NTSC)
Display resolution	32x26.5 patterns (256x212 pixels)	64x26.5 patterns (512x212 pixels)
Image space	64x64 patterns	128x64 patterns
Number of layers	2 layers with priority control	1 layer
Pattern size	8x8 pixels	8x8 pixels
Simultaneously displayed colors	30 colors + transparant	30 colors + transparant
Color palette	4 palettes of 16 colors out of 32768 colors	4 palettes of 16 colors out of 32768 colors
Number of patterns	Layer "A": 8160 units Layer "B": 7680 units	15360 units

Sprite Display Function

Size	16x16 pixels
Limited No. of displayed units	125 on 1 screen 16 on 1 line
Displayed colors	15 colors + clear color (for each pixel) Palette can be selected for each sprite (1 palette selected out of 4)
Specification of display priority	Priority between sprite and pattern layer can be set for each sprite. The sprite No. order is used for priority order among sprites.
Pattern	Selected from among 256 patterns The pattern data is shared with the pattern layer (the base address should be set in register R#25.)

Bit map screen display function

Mode	Master clock (MHz)	Pixel clock (MHz)	Display resolution () interlaced (pixel x pixel)	Color depth (bits per pixel)	Image size by width (lines)
					256 pixels	512 pixels	1024 pixels	2048 pixels
*B0	14.3	3.6	Overscan NTSC 192x240 (192x480) Overscan PAL 192x290 (192x580)	16	1024	512	256
				8	2048	1024	512	256
				4	4096	2048	1024	512
				2	8192	4096	2048	1024
B1	21.5	5.4	NTSC/PAL 256x212 (256x424)	16	1024	512	256
				8	2048	1024	512	256
				4	4096	2048	1024	512
				2	8192	4096	2048	1024
B2	14.3	7.2	Overscan NTSC 384x240 (384x480) Overscan PAL 384x290 (384x580)	16		512	256
				8		1024	512	256
				4		2048	1024	512
				2		4096	2048	1024
B3	21.5	10.7	NTSC/PAL 512x212 (512x424)	16		512	256
				8		1024	512	256
				4		2048	1024	512
				2		4096	2048	1024
B4	14.3	14.3	Overscan NTSC 768x240 (768x480) Overscan PAL 768x290 (768x580)	4			1024	512
				2			2048	1024
B5	21.5	21.5	640x400 @ 25.3kHz	4			1024	512
				2			2048	1024
B6	25.2	25.2	640x480 @ 31.5kHz	4			1024	512
				2			2048	1024
*B7	21.5	21.5	NTSC/PAL 1024x212 (1024x424)	4			1024	512
				2			2048	1024
* Undocumented mode

Displayed color (RGB conversion system)

bits per pixel	Name	RGB conversion system	Number of displayed colors
16	BD16	Direct RGB (YS:1bit, G:5bit, R:5bit, B:5bit)	32768 colors
8	BD8	Direct RGB (G:3bit,R:3bit,B:2bit)	256 colors
	BYJK	YJK Decoder	19268 colors
	BYJKP	YJK Decoder + Color palette	12599 colors + 16 colors out of 32768 colors
	BYUV	YUV Decoder	19268 colors
	BYUVP	YUV Decoder + Color palette	12599 colors + 16 colors out of 32768 colors
	BP6	Color palette	64 colors out of 32768 colors
4	BP4	Color palette	16 colors out of 32768 colors
2	BP2	Color palette	4 colors out of 32768 colors

Cursor Function

Size Number of displayed units Displayed color Pattern	32x32 pixels 2 in 1 screen 3 colors + EOR color on bit map screen + clear color Any form

Mode	P#7	R#6				R#7
	MCS	DSPM	DCKM	XIMM	CLRM	C25M	SM1	SM	PAL	EO	IL	HSCN
P1	0	0	0	1	1	0	0/1	0/1	0/1	0/1	0/1	0
P2	0	1	1	2	1	0	0/1	0/1	0/1	0/1	0/1	0
*B0	1	2	0	0-3	0-3	0	0/1	0/1	0/1	0/1	0/1	0
B1	0	2	0	0-3	0-3	0	0/1	0/1	0/1	0/1	0/1	0
B2	1	2	1	1-3	0-3	0	0/1	0/1	0/1	0/1	0/1	0
B3	0	2	1	1-3	0-3	0	0/1	0/1	0/1	0/1	0/1	0
B4	1	2	2	2-3	0-1	0	0/1	0/1	0/1	0/1	0/1	0
B5	0	2	2	2-3	0-1	0	0	0	0	0	0	1
B6	0	2	2	2-3	0-1	1	0	0	0	0	0	1
*B7	0	2	2	2-3	0-1	0	0/1	0/1	0/1	0/1	0/1	0
* Undocumented mode

Display type when the display mode is P1 or P2

Sprite colors are specified by Pattern data plus a palette offset specified in the Sprite Attribute Table.

Background colors are specified by Pattern data plus a palette offset in R#13. P1 layer "A" and P2 pattern pixels 0,1,4,5 use offset specified in R#13 PLTO3-2. P1 layer "B" and P2 pattern pixels 2,3,6,7 use offset specified in R#13 PLTO5-4.

Display type when the display mode uses full YJK on the bit map. This mode is the same as V9958 YJK mode.

Cursor colors are specified by the Cursor Attribute Table plus a palette offset specified by R#28 CSPO5-2.

Background colors are specified by YJK bitmap data. Base color, specified by JK values, is shared among 4 pixels, each pixel has an individual Y (luminance) value.

	b7	b6	b5	b4	b3	b2	b1	b0
1st pixel	Y					K (low)
2nd pixel	Y					K (high)
3rd pixel	Y					J (low)
4th pixel	Y					J (high)

RGB-YJK conversion:

R = Y + J	Y = B/2 + R/4 + G/8
G = Y + K	J = R - Y
B = 5/4Y - J/2 - K/4	K = G - Y

Display type when the display mode uses YJK and palette mixed on the bit map. This mode is the same as V9958 YJKP (aka YAE) mode.

Same as BYJK, except that for each pixel bit A selects YJK or Palette mode. In Palette mode, colors are specified by Y value plus a palette offset specified in R#13 PLTO5-4.

	b7	b6	b5	b4	b3	b2	b1	b0
1st pixel	Y				A	K (low)
2nd pixel	Y				A	K (high)
3rd pixel	Y				A	J (low)
4th pixel	Y				A	J (high)

Display type when the display mode uses full YUV on the bit map

Same as BYJK, but GREEN and BLUE channels are swapped, often resulting in better image quality.

	b7	b6	b5	b4	b3	b2	b1	b0
1st pixel	Y					V (low)
2nd pixel	Y					V (high)
3rd pixel	Y					U (low)
4th pixel	Y					U (high)

RGB-YUV conversion:

R = Y + U	Y = G/2 + R/4 + B/8
G = 5/4Y - U/2 - V/4	U = R - Y
B = Y + V	V = B - Y

Display type when the display mode uses YUV and palette mixed on the bit map

Same as BYJKP, but GREEN and BLUE channels are swapped, often resulting in better image quality.

	b7	b6	b5	b4	b3	b2	b1	b0
1st pixel	Y				A	V (low)
2nd pixel	Y				A	V (high)
3rd pixel	Y				A	U (low)
4th pixel	Y				A	U (high)

Display type when the display mode uses 16 bit data directly on the bit map (5 bits for each RGB plus Ys)

Cursor colors are specified by the Cursor Attribute Table plus a palette offset specified by R#28 CSPO5-2.

Background data are specified in 16 bit as follows.

	b7	b6	b5	b4	b3	b2	b1	b0
1st byte	R (bit 2-0)			B
2nd byte	Ys	G					R (bit 4-3)

Display type when the display mode uses 8 bit data directly on the bit map (3, 3, 2 bits for each RGB, Ys at ALL 0)

Cursor colors are specified by the Cursor Attribute Table plus a palette offset specified by R#28 CSPO5-2.

Background data are specified in 8 bit as follows.

	b7	b6	b5	b4	b3	b2	b1	b0
	G			R			B

Although this mode is similar to the RGB332 mode of V9938, because of the way these values are mapped on the 15 bit palette, the resulting colors will differ slightly. For instance, pure grey is not possible.

RED and GREEN
3 bit value	7	6	5	4	3	2	1	0
Palette value	31	27	22	18	13	9	4	0
BLUE
2 bit value	3		2		1			0
Palette value	31		21		11			0

Display type when the display mode uses 8 bit data on the bit map through the palette

Cursor colors are specified by the Cursor Attribute Table plus a palette offset specified by R#28 CSPO5-2.

Background colors are specified by a 6 bit palette value, bits 7-6 are ignored.

Display type when the display mode uses 4 bit data and offset 2 bits on the bit map through the palette

Cursor colors are specified by the Cursor Attribute Table plus a palette offset specified by R#28 CSPO5-2.

Background colors are specified by a 4 bit value plus a palette offset specified in R#13 PLTO5-4.

Note: When setting the color palette data in the B4, B5 and B6 modes, use the same value for each corresponding pair of palette addresses 0 to 31 and 32 to 63, that is, 0 and 32, 1 and 33 and so on.

Display type when the display node uses 2 bit data and offset 4 bits on the bit map through the palette

Cursor colors are specified by the Cursor Attribute Table plus a palette offset specified by R#28 CSPO5-2.

Background colors are specified by a 2 bit value plus a palette offset specified in R#13 PLTO5-2.

Note: When setting the color palette data in the B4, B5 and B6 modes, use the same value for each corresponding pair of palette addresses 0 to 31 and 32 to 63, that is, 0 and 32, 1 and 33 and so on.

PALETTE CONTROL (WRITE ONLY)

	b7	b6	b5	b4	b3	b2	b1	b0
R#13	PLTM		YAE	PLTAIH	PLTO5	PLTO4	PLTO3	PLTO2

CURSOR SPRITE PALETTE OFFSET (WRITE ONLY)

	b7	b6	b5	b4	b3	b2	b1	b0
R#28	0	0	0	0	CSPO5-2

BACK DROP COLOR (READ/WRITE)

	b7	b6	b5	b4	b3	b2	b1	b0
R#15	0	0	BDC5	BDC4	BDC3	BDC2	BDC1	BDC0

SCREEN MODE (READ/WRITE)

	b7	b6	b5	b4	b3	b2	b1	b0
R#6	DSPM		DCKM		XIMM		CLRM

	DSPM	PLTM	CLRM	YAE
(1) PP	0,1	0	1	-
(2) BYJK	2	2	2	0
(3) BYJKP	2	2	2	1
(4) BYUV	2	3	2	0
(5) BYUVP	2	3	2	1
(6) BD16	2	0	3	-
(7) BD8	2	1	2	-
(8) BP6	2	0	2	-
(9) BP4	2	0	1	-
(10) BP2	2	0	0	-

Physical mapping: Addresses 00000-3FFFF in VRAM0 and 40000-7FFFF in VRAM1.

00000-3FDFF	(Sprite) Pattern Data (Layer A)
3FE00-3FFFF	Sprite Attribute Table
40000-7BFFF	Pattern Data (Layer B)
7C000-7DFFF	PNT(A) - Pattern Name Table (Layer A)
7E000-7FFFF	PNT(B) - Pattern Name Table (Layer B)

Pattern Data is layed out like a 4bpp bitmap with 256 pixel width, cut up in 8x8 patterns. Pattern 0 1st line starts at 00000, Pattern 0 2nd line starts at 00080 etc., Pattern 1 1st line starts at 00004 etc., Pattern 32 1st line starts at 00400 etc.

Sprite Pattern Data is shared with background Pattern Data, but 16x16 Patterns are used.

The Name Table describes the entire Image Space, each Pattern is specified by a 16 bit value.

Physical mapping: Pattern Data even addresses (bit0=0) in VRAM0 and odd addresses (bit0=1) in VRAM1, Sprite Attribute Table in VRAM0 and PNT in VRAM1.

00000-77FFF	(Sprite) Pattern Data
78000-7BDFF	-
7BE00-7BFFF	Sprite Attribute Table
7C000-7FFFF	PNT

Pattern Data is layed out like a 4bpp bitmap with 512 pixel width, cut up in 8x8 patterns. Pattern 0 1st line starts at 00000, Pattern 0 2nd line starts at 00100 etc., Pattern 1 1st line starts at 00004 etc., Pattern 64 1st line starts at 00800 etc.

Sprite Pattern Data is shared with background Pattern Data, but 16x16 Patterns are used.

The Name Table describes the entire Image Space, each Pattern is specified by a 16 bit value.

Physical mapping: even addresses (bit 0=0) in VRAM0 and odd addresses (bit0=1) in VRAM1.

00000-7FDFF	Bitmap Data
7FE00-7FFFF	Cursor area (512 bytes)

Sprite size is 16x16, 125 sprites can be specified in the Sprite Attribute Table.

Up to 16 sprites can be displayed on one horizontal line.

• Sprite Priority

Each sprites can be displayed in front or behind of the front layer.

Sprites that are listed first in the Sprite Attribute Table have a higher priority than those listed last.

• Sprite Coordinate Space

Sprites exist in a seperate coordinate space from normal image space. Sprite coordinate (0,0) is always the top-left of the display area. The Sprite coordinate space is 1024x256 and display wrapping is done along its edges.

• Sprite Attribute Table

	b7	b6	b5	b4	b3	b2	b1	b0
Offset +0	Y
Offset +1	PAT
Offset +2	X (bit 7-0)
Offset +3	SC5-4		P	D	-	-	X (bit 9-8)

Y	: Sprite Y-coordinate (Actual display position is one line below specified)
X	: Sprite X-coordinate
PAT	: Sprite Pattern Number (Pattern Offset is specified in R#25 SGBA)
P	: Sprite is in front of the front layer when P=0, sprite is behind the front layer when P=1.
D	: Sprite is disabled when D=1
SC5-4	: Palette offset for sprite colors.

Even though there is room for 128 sprite entries, only the first 125 are functional. The extra 12 bytes are unused by the VDP and can be used at the programmer's discretion.

Cursor size is 32x32, 2 cursors can be specified and displayed on screen.

When using a cursor (enabled in R#8 SPD), 512 bytes from the upper address of VRAM (7FE00-7FFFF) are used as the data area for the cursor. Display is also possible in this area, no skipping occurs during display.

• Cursor Coordinate Space

Cursors exist in a seperate coordinate space from normal image space. Cursor coordinate (0,0) is always the top-left of the display area. The Cursor coordinate space is 1024x512 and display wrapping is done along its edges.

• Cursor Attribute Table

	b7	b6	b5	b4	b3	b2	b1	b0
7FE00	Y (bit 7-0)
7FE02	-	-	-	-	-	-	-	Y (bit 8)
7FE04	X (bit 7-0)
7FE06	CC1-0		EOR	D	-	-	X (bit 9-8)
+8 for 2nd cursor

Y	: Cursor Y-coordinate (Actual display position is one line below specified, two lines for interlace)
X	: Cursor X-coordinate
D	: Cursor is disabled when D=1
CC1-0	: Cursor Color value (Added to palette offset specified in R#28 CSPO5-2). If CC1-0=0 and EOR=0, clear color is used.
EOR	: Cursor is displayed on screen with EOR color when EOR=1 and CC1-0=0

• Cursor Pattern Table

Cursor Pattern Table is located at 7FF00 (7FF80 for 2nd cursor).

Cursor pattern is specified by a bit pattern of 128 bytes. Each bit is a pixel, and each line of 32 pixels is specified in 4 consecutive bytes.

After setting the necessary parameter register, set the command to the operation code register, and it will be executed. As soon as execution is started, the status CE is set to "1" and upon completion, it is reset to "0". Furthermore, the interrupt flag CE is set to "1".

Most commands are issued after the necessary registers out of the following parameters are set. Also some commands require output and input of the necessary data at and through the command data port after they are issued.

1. Source (for transfer) coordinate
2. Destination (for transfer) coordinate
3. Transfer range coordinates
4. Argument, logical operation and Write Mask
5. Font color

The following commands are available:

Opcode	Mnemonic	Operation
0	STOP	Command being executed is stopped.
1	LMMC	Data is transferred from CPU to VRAM rectangle area.
2	LMMV	VRAM rectangle area is painted out.
3	LMCM	VRAM rectangle area data is transferred to CPU.
4	LMMM	Rectangle area data is transferred from VRAM to VRAM.
5	CMMC	CPU character data is color-developed and transferred to VRAM rectangle area.
7	CMMM	VRAM character data is color-developed and transferred to VRAM rectangle area.
8	BMXL	Data on VRAM linear address is transferred to VRAM rectangle area.
9	BMLX	VRAM rectangle area data is transferred onto VRAM linear address.
10	BMLL	Data on VRAM linear address is transferred onto VRAM linear address.
11	LINE	Straight line is drawn on X/Y-coordinates.
12	SEARCH	Border color coordinates on X/Y space are detected.
13	POINT	Color code of specified point on X/Y-coordinates is read out.
14	PSET	Drawing is executed at drawing point on X/Y-coordinates.
15	ADVANCE	Drawing point on X/Y-coordinates is shifted.

Any command that writes to VRAM is using a Logical Operation (LOP) and a Write Mask (WM), specified as follows.

• Logical Operation

	b7	b6	b5	b4	b3	b2	b1	b0
R#45	0	0	0	TP	L11	L10	L01	L00

WC (Write Color) is obtained through logical operation with SC (Source Color) and DC (Destination Color). The logical operation can be constructed as follows:

L00	: WC value for the bit with SC=0 and DC=0.
L01	: WC value for the bit with SC=0 and DC=1.
L10	: WC value for the bit with SC=1 and DC=0.
L11	: WC value for the bit with SC=1 and DC=1.
TP	: When this bit is "1", the data with SC as all "0" (by pixel for the X/Y-coordinates and by byte for the linear address) is not transferred.

<Example>

Logical Operation	L11	L10	L01	L00
WC = SC	1	1	0	0
WC = SC	0	0	1	1
WC = SC AND DC	1	0	0	0
WC = SC OR DC	1	1	1	0
WC = SC EOR DC	0	1	1	0

• Write Mask

	b7	b6	b5	b4	b3	b2	b1	b0
R#46	WM (bit 7-0)
R#47	WM (bit 15-8)

When drawing by means of commands, writing can be prohibited by bits. With WM (bit 7-0) and WM (bit 15-8), VRAM0 bit and VRAM1 bit are specified respectively. Then "1" is for write enable and "0" is for write prohibit.

In P1 mode, writing is prohibited on the side not specified as the transfer destination. (Layer "A":R#46, Layer "B":R#47)

Transfer data from CPU to VRAM rectangle area.

Set DX, DY, NX, NY, DIY, DIX and finally OP.

Output the necessary number of bytes to the command data port (P#2) as follows.

2bpp	b7	b6	b5	b4	b3	b2	b1	b0
1st byte	1st pixel		2nd pixel		3rd pixel		4th pixel
2nd byte	5th pixel		6th pixel		7th pixel		8th pixel
	...

4bpp	b7	b6	b5	b4	b3	b2	b1	b0
1st byte	1st pixel				2nd pixel
2nd byte	3rd pixel				4th pixel
	...

8bpp	b7	b6	b5	b4	b3	b2	b1	b0
1st byte	1st pixel
2nd byte	2nd pixel
	...

16bpp	b7	b6	b5	b4	b3	b2	b1	b0
1st byte	1st pixel color code low
2nd byte	1st pixel color code high
3rd byte	2nd pixel color code low
	...

The VRAM rectangle area is painted out by using the color code.

Set DX, DY, NX, NY, DIY, DIX, FC finally and OP.

The data of the rectangle area in VRAM is transferred to CPU.

Set SX, SY, NX, NY, DIY, DIX and finally OP.

After this, the data for necessary number of bytes is read from the command data port (P#2). See LMMC for data format.

The rectangle area data is transferred from VRAM to VRAM.

Set SX, SY, DX, DY, NX, NY, DIY, DIX and finally OP.

The data for each character is transferred from CPU to the rectangle area in VRAM.

Set DX, DY, NX, NY, DIY, DIX, FC, BC and finally OP.

Output the necessary number of bytes to the command data port (P#2).

The character data is similar to the MSX kanji ROM. It's provided in the order of upper left, upper right, lower left and lower right blocks (8 bytes each) of the 16x16 font.

1st 8 bytes	2nd 8 bytes	Font : 16 pixels vertical x 16 pixels horizontal
3rd 8 bytes	4th 8 bytes

Data for each character is transferred from VRAM linear address to VRAM rectangle area.

Set SA, DX, DY, NX, NY, DIY, DIX, FC, BC and finally OP.

Data format is the same as for CMMC.

The data on the linear address in VRAM is transferred to the rectangle area.

Set SA, DX, DY, NX, NY, DIY, DIX and finally OP.

The data of the rectangle area in VRAM is transferred onto the linear address.

Set SX, SY, DA, NX, NY, DIY, DIX and finally OP.

The data on the linear address in VRAM is transferred onto the linear address.

Set SA, DA, NA, DIY, DIX and finally OP.

Note: BMLL operates on interleaved VRAM (as in B-modes) always, so that must be taken into account for using it in P1 or areas of P2. This means that source and destination addresses must be rotated one left and the correct Write Mask must be set.

A straight line is drawn from the reference point on VRAM.

Set DX, DY, MJ, MI, DIY, DIX, MAJ, FC and finally OP.

A border color (or non-border color) is searched for toward the right (or left) of the base point on VRAM.

Set SX, SY, DIX, NEQ, FC and finally OP.

Afterwards, BX (R#53,54) contains the border X-coordinate.

The color code at the base point on VRAM is read out.

Set SX, SY and finally OP.

The (SX,SY) color code can now be read from the command data port (P#2) as follows.

2bpp	b7	b6	b5	b4	b3	b2	b1	b0
	color code		unspecified

4bpp	b7	b6	b5	b4	b3	b2	b1	b0
	color code				unspecified

8bpp	b7	b6	b5	b4	b3	b2	b1	b0
	color code

16bpp	b7	b6	b5	b4	b3	b2	b1	b0
1st byte	color code low
2nd byte	color code high

A point is drawn on VRAM. After that, the pointer can be advanced.

Set DX, DY, FC and finally OP, AYM, AYE, AXM and AXE.

DX, DY should not be set when using the current pointer.

The drawing pointer is moved.

Set DX, DY, and finally OP, AYM, AYE, AXM and AXE.

DX, DY should not be set when using the current pointer.

P#0	VRAM DATA	(R/W)
P#1	PALETTE DATA	(R/W)
P#2	COMMAND DATA	(R/W)
P#3	REGISTER DATA	(R/W)
P#4	REGISTER SELECT	(W)
P#5	STATUS	(R)
P#6	INTERRUPT FLAG	(R/W)
P#7	SYSTEM CONTROL	(W)
P#8-B	Kanji ROM
P#C-F	Reserved

• VRAM DATA PORT (READ/WRITE)

	b7	b6	b5	b4	b3	b2	b1	b0
P#0	VRAM Data

• The data written in this port is written in the VRAM address specified by using R#0 to R#3. If writing to this port has taken place before completion of data write in VRAM, a WAIT signal is output.
• By reading through this port, the VRAM address data specified by using R#3 to R#5 is obtained. If reading has taken place at this port before data preparation, a WAIT signal is output. When VRAM read address has been modified to prepare the VRAM address data at completion of data write to R#5, it must be written in R#5.

• PALETTE DATA PORT (READ/WRITE)

	b7	b6	b5	b4	b3	b2	b1	b0
P#1	Palette Data

• The data written in this port is written in the internal palette RAM.
• By reading through this port, the internal palette RAM data can be obtained. A WAIT signal is output till the data has been prepared.
• The palette RAM address is specified by using R#14.
• The data format is as follows.

	b7	b6	b5	b4	b3	b2	b1	b0
RED	YS	-	-	R4	R3	R2	R1	R0
GREEN	-	-	-	G4	G3	G2	G1	G0
BLUE	-	-	-	B4	B3	B2	B1	B0

• COMMAND DATA PORT (READ/WRITE)

	b7	b6	b5	b4	b3	b2	b1	b0
P#2	Command Data

• The command data is read and written through this port. Access to this port when the status TR bit is "0" while the command is being executed will result in an output of WAIT signal.

• REGISTER DATA PORT (READ/WRITE)

	b7	b6	b5	b4	b3	b2	b1	b0
P#3	Register Data

• The data written in this port is written in the register specified by using P#4.
• By reading through this port, the register data specified by using P#4 can be obtained.

• REGISTER SELECT PORT (WRITE ONLY)

	b7	b6	b5	b4	b3	b2	b1	b0
P#4	WII	RII	Register No.

• Register No. specifies which register is accessed via P#3.
• The Register No. undergoes a plus "1" increment through P#3 access. However, when WII is "1", increment in writing at P#3 is prohibited and when RII is "1", increment in reading at P#3 is prohibited.

• STATUS PORT (READ ONLY)

	b7	b6	b5	b4	b3	b2	b1	b0
P#5	TR	VR	HR	BD	0	MCS	EO	CE

• Various types of status data can be read out as follows.
  • TR : Command data transfer ready. It is reset through P#2 access.
  • VR : Vertical non-display period. It is set when the drawing of VRAM content has stopped.
  • HR : Horizontal non-display period
  • BD : Border color detect at completion of SRCH command (becomes "1" when detected)
  • EO : In the second field period during interlace
  • CE : Command being executed
  • MCS: Content of P#7 MCS

• INTERRUPT FLAG PORT (READ/WRITE)

	b7	b6	b5	b4	b3	b2	b1	b0
P#6	0	0	0	0	0	CE	HI	VI

• The interrupt flags can be read out as follows.
  • CE : Command completion flag
  • HI : Display position flag
  • VI : Vertical display period completion flag
• By writing "1", the related bit flag is reset.

• SYSTEM CONTROL (WRITE ONLY)

	b7	b6	b5	b4	b3	b2	b1	b0
P#7	0	0	0	0	0	0	SRS	MCS

• SRS : Writing "1" will set all ports except this one in "power ON reset" state. "0" should be written to cancel it.
• MCS : The internally used master clock is selected.
  • 1 : MCKIN terminal
  • 0 : XTAL1 terminal

NOTE) XTAL1 terminal is selected when "power ON reset".

R#0-2	VRAM WRITE ADDRESS	(W)
R#3-5	VRAM READ ADDRESS	(W)
R#6,7	SCREEN MODE	(R/W)
R#8	CONTROL	(R/W)
R#9-12	INTERRUPT	(R/W)
R#13	PALETTE CONTROL	(W)
R#14	PALETTE POINTER	(W)
R#15	BACK DROP COLOR	(R/W)
R#16	DISPLAY ADJUST	(R/W)
R#17-24	SCROLL CONTROL	(R/W)
R#25	SPRITE GENERATOR BASE ADDRESS	(R/W)
R#26	LCD CONTROL	(R/W)
R#27	PRIORITY CONTROL	(R/W)
R#28	CURSOR SPRITE PALETTE OFFSET	(W)
R#32-52	COMMAND	(W)
R#53,54	COMMAND	(R)

• VRAM WRITE ADDRESS (WRITE ONLY)

	b7	b6	b5	b4	b3	b2	b1	b0
R#0	VRAM Write Address (bit 7-0)
R#1	VRAM Write Address (bit 15-8)
R#2	AII	0	0	0	0	VRAM Write Address (bit 18-16)

AII	=0 : VRAM Write Address undergoes an increment of plus "1" only at the end of writing to P#0.
	=1 : No increment.

• VRAM READ ADDRESS (WRITE ONLY)

	b7	b6	b5	b4	b3	b2	b1	b0
R#3	VRAM Read Address (bit 7-0)
R#4	VRAM Read Address (bit 15-8)
R#5	AII	0	0	0	0	VRAM Read Address (bit 18-16)

AII	=0 : VRAM Read Address undergoes an increment of plus "1" only at the end of reading at P#0.
	=1 : No increment.

• SCREEN MODE (READ/WRITE)

	b7	b6	b5	b4	b3	b2	b1	b0
R#6	DSPM		DCKM		XIMM		CLRM
R#7	0	C25M	SM1	SM	PAL	EO	IL	HSCN

DSPM	Display mode selection
3	: Stand-by mode (non-display, no VRAM refresh, kanji ROM readable)
2	: Bit map mode (Bl-6)
1	: P2 mode
0	: P1 mode

DCKM	Pixel clock selection (used in combination with MCS of P#7)
	MCS=0	MCS=1
2	: XTAL1	MCKIN
1	: XTAL1/2	MCKIN/2
0	: XTAL1/4	*MCKIN/4	(Number of division of master clock)
* Undocumented setting

XIMM	Selection of number of pixels in X direction of image space (Number of pixels in Y direction is automatically calculated from XIMM and CLRM)
3	: 2048 pixels
2	: 1024 pixels
1	: 512 pixels
0	: 256 pixels

CLRM	Selection of bit number per pixel
3	: 16 bits/pixel
2	: 8 bits/pixel
1	: 4 bits/pixel
0	: 2 bits/pixel

C25M	Selection of 640X480 mode, valid when HSCN is "1".
1	: B6 mode
0	: other modes

SM1	Selection of total number of vertical lines during non-interlace, NTSC
1	: 263 lines (In combination with SM, the sub-carrier phase is inverted for each frame.)
0	: 262 lines

SM	Selection of horizontal frequency (invalid when in B5 and B6 modes)
1	: 1H=fsc/227.5 (the sub-carrier phase is inverted for each line.)
0	: 1H=fsc/228

PAL	Selection of PAL mode (invalid when in B5 and B6 modes)
1	: Vertical frequency becomes PAL specification.
0	: Vertical frequency becomes NTSC specification.

EO	Selection of vertical resolution during interlace (invalid when in B5 and B6 modes)
1	: Twice the vertical resolution during non-interlace
0	: Same as during non-interlace

IL	Selection of interlace mode (invalid when in B5 and B6 modes)
1	: Interlace
0	: Non-interlace

HSCN	Selection of horizontal high scan mode
1	: B5, B6 modes
0	: other modes

• CONTROL (READ/WRITE)

	b7	b6	b5	b4	b3	b2	b1	b0
R#8	DISP	SPD	YSE	VWTE	VWM	0	1	0

DISP	Screen display enable
1	: Display appears on screen according to the VRAM content.
0	: Back drop color is displayed all over the screen.

SPD	Sprite (cursor) Disable
1	: Sprite (cursor) is not displayed.
0	: Sprite (cursor) is displayed.

YSE	YS signal output enable
1	: YS signal is output.
0	: YS signal is not output. (YS terminal constantly remains as low level.)

VWTE	VRAM serial data bus input/output control during digitization
1	: Dummy write transfer is executed during horizontal retrace line interval. (The serial data bus of VRAM becomes an input terminal.)
0	: Read transfer is executed during horizontal retrace line interval. (The serial data bus of VRAM becomes an output terminal.)

VWM	VRAM write control during digitization
1	: Write transfer is executed during horizontal retrace line interval. (The data input into the serial data bus of VRAM during display period undergoes write transfer.)
0	: Write transfer is not executed.

• INTERRUPT (READ/WRITE)

	b7	b6	b5	b4	b3	b2	b1	b0
R#9	0	0	0	0	0	IECE	IEH	IEV
R#10	Interrupt Line (bit 7-0)
R#11	IEHM	0	0	0	0	0	Interrupt Line (bit 9-8)
R#12	0	0	0	0	Interrupt X

IECE	Command end interrupt enable control
1	: INT0 terminal becomes low level when CE flag of P#6 is "1".
0	: INT0 terminal does not change according to CE flag.

IEV	Interrupt enable during vertical retrace line interval.
1	: INT0 terminal becomes low level when VI flag of P#6 is "1".
0	: INT0 terminal does not change according to VI flag.

IEH	Display position interrupt enable (Interrupt position is specified with Interrupt Line, Interrupt X and IEHM.)
1	: INT1 terminal becomes low level when HI flag of P#6 is "1".
0	: INT1 terminal does not change according to HI flag.

Interrupt Line	: Specification of vertical position where display position interrupt occurs (Specified by means of line No. with the display start line as "0".)

Interrupt X	: Specification of horizontal position where display position interrupt occurs (Specified by unit of 64 master clock with the display start position as "0".)

IEHM	Selection of vertical position for display position interrupt
1	: Every line (value of Interrupt Line is ignored)
0	: Specified line

• PALETTE CONTROL (WRITE ONLY)

	b7	b6	b5	b4	b3	b2	b1	b0
R#13	PLTM		YAE	PLTAIH	PLTO5	PLTO4	PLTO3	PLTO2

PLTM	Selection of color palette mode
3	: YUV mode
2	: YJK mode
1	: 256 color mode
0	: Palette mode

YAE	Selection of YJK (YUV) and RGB mixing mode (valid when in YUV and YJK modes)
1	: YJK (YUV) and RGB images are displayed together.
0	: Only YJK (YUV) image is displayed.

PLTAIH	Palette No. increment control at color palette read-out
1	: R#14 palette pointer is not changed by P#1 read-out.
0	: After P#1 read-out, R#14 palette pointer undergoes an increment.

PLTO5-2	: Still screen palette No. offset

• PALETTE POINTER (WRITE ONLY)

	b7	b6	b5	b4	b3	b2	b1	b0
R#14	PLTA						PLTP

PLTA	: Palette No.(color code)

PLTP	Specification of RGB
2	: BLUE
1	: GREEN
0	: RED
After completion of access to P#1, an increment takes place by plus 1 only. PLTP is used as a 0 to 2 ternary counter.

• BACK DROP COLOR (READ/WRITE)

	b7	b6	b5	b4	b3	b2	b1	b0
R#15	0	0	BDC

BDC	: Palette No. of back drop color

• DISPLAY ADJUST (READ/WRITE)

	b7	b6	b5	b4	b3	b2	b1	b0
R#16	ADJV				ADJH

ADJV	: Vertical display position adjustment (4 bit signed)	8 9 ... 15	0	1 ... 6 7
	(by line)	Down	Center	Up
ADJH	: Horizontal display position adjustment (4 bit signed)	8 9 ... 15	0	1 ... 6 7
		Right	Center	Left
(P1 and B1 by 1 pixel unit, P2, B2 and B3 by 2-pixel unit, B4, B5 and B6 by 4-pixel unit)

• SCROLL CONTROL (READ/WRITE)

	b7	b6	b5	b4	b3	b2	b1	b0
R#17	SCAY (bit 7-0)
R#18	R512	R256	0	SCAY (bit 12-8)
R#19	0	0	0	0	0	SCAX (bit 2-0)
R#20	SCAX (bit 10-3)
R#21	SCBY (bit 7-0)
R#22	*SDA	*SDB	0	0	0	0	0	SCBY (bit 8)
R#23	0	0	0	0	0	SCBX (bit 2-0)
R#24	0	0	SCBX (bit 8-3)
* Undocumented setting

SCAY SCAX	: As display start coordinates for layer "A" of P1 mode and screens of other modes, X/Y-coordinates in the image space are specified by pixels. (When 16bpp is used in B2 and B3 modes, however, bit 0 is ignored and X-coordinate is specified by 2-pixel unit.)
SCBY SCBX	: For layer "B" of P1, X/Y-coordinates are specified in the same way as for SCAX/SCAY.

R512	R256	Number of roll page line in Y direction is specified.
1	0	: Displayed page is rolled by 512 lines.
0	1	: Displayed page is rolled by 256 lines.
0	0	: Rolling by image space size takes place.

SDA	: Set to "1" to disable layer "A" and sprites.
SDB	: Set to "1" to disable layer "B" and sprites.

• SPRITE GENERATOR BASE ADDRESS (READ/WRITE)

	b7	b6	b5	b4	b3	b2	b1	b0
R#25	0	0	0	0	SGBA17	SGBA16	SGBA15	0	P1 mode
	0	0	0	0	SGBA18	SGBA17	SGBA16	SGBA15	P2 mode

SGBA18-15	: Base address of P1/P2 mode sprite pattern data

• LCD CONTROL (READ/WRITE)

Omitted (keep register R#26 as 0)

• PRIORITY CONTROL (READ/WRITE)

	b7	b6	b5	b4	b3	b2	b1	b0
R#27	0	0	0	0	PRY		PRX

PRY	: When in P1 mode, the display Y-coordinate to exchange display priority order between layers "A" and "B" is specified. A unit of 64 lines is used and in the range lower than the specified line (including that line), layer "B" has priority. At "0", layer "A" has priority throughout the range.
PRX	: When in P1 mode, the display X-coordinate to exchange display priority order between layers "A" and "B" is specified. A unit of 64 pixels is used and in the range to the right of the specified pixel (including that pixel), layer "B" has priority. At "0", layer "A" has priority throughout the range.

<Example> When PRX=2 and PRY=2

		1	2	3	0	(PRX)
	0	64	128	192	256	(pixel)
1	64	A	A	B	B
2	128	A	A	B	B
3	192	B	B	B	B
0	256	B	B	B	B	(211)
(PRY)	(pixel)

• CURSOR SPRITE PALETTE OFFSET (WRITE ONLY)

	b7	b6	b5	b4	b3	b2	b1	b0
R#28	0	0	0	0	CSPO5-2

CSPO5-2	: Palette No. offset of cursor

COMMAND PARAMETER (WRITE ONLY, READ ONLY)